The present invention relates generally to a phase-locked loop for data recovery, and more particularly, to a multi-phase-locked loop that utilizes a multi-phase clock signal generated by a multi-phase voltage controlled oscillator (VCO) to detect received data.
Due to the development of the network transmission technology as well as the demands in the installed base of computer networks, the network data transmission rate in hardware environment has been increased. Therefore, it becomes more and more important to recover data (clock signals) correctly.
At present, while data (clock) recovery is to be performed, a phase-locked loop is often utilized. During the data recovery process, usually the received data could be correctly recovered (read) by using a phase detector to synchronize the received data and recover the clock. In other words, the phase detector plays a very important role whether the data could be correctly recovered by a phase-locked loop.
FIG. 1 illustrates a prior art phase-locked loop for data recovery comprising a phase detector 11, a charge pump 12, a loop filter 13, and a voltage controlled oscillator 14. The phase detector 11 is used to receive a data (clock) signal from outside as well as a feedback clock signal CKvco from the voltage controlled oscillator 14. The phase detector 11 compares the two signals, in accordance with their phase difference xcex8e (xcex8e=xcex8dataxe2x88x92xcex8clock), a control signal up or dn will be output to control the charge pump 12. As shown in FIG. 2(a), when the transition edge of the data (clock) signal data leads the falling edge of the feedback clock signal CKvco, the phase detector outputs an up signal. On the other hand, as shown in FIG. 2(b), when the transition edge of the data (clock) signal data lags behind the falling edge of the feedback clock signal CKvco, the phase detector 11 outputs a dn signal. The charge pump 12 is controlled by the up and dn control signals output from the phase detector 11 to perform charge/discharge operations, and generates a voltage signal Vd. The loop filter 13 receives the voltage signal Vd and generates an appropriate voltage Vc for controlling the voltage controlled oscillator 14. The voltage controlled oscillator 14 receives the voltage Vc and generates a clock signal CKvco to be input to the phase detector 11.
As shown in FIG. 3, the phase detector 11 of the phase locked loop 1 is constituted by four flip-flops 111, 112, 113,114, and two OR gates 115, 116. The flip-flops 111 and 112 receive the complement of data from outside (denoted by {overscore (data)}) and the data itself (denoted by data), respectively. The clock signal CKvco from the voltage controlled oscillator 14 is applied to the inversion reset terminals (rb) of the flip-flops 111 and 112 such that two control signals up1 and up2 are generated, respectively. The flip-flops 113 and 114 receive the complement of data from outside (denoted by {overscore (data)}) and the data itself (denoted by data), respectively. The complement of the clock signal CKvco (denoted by {overscore (CKvco+L )}) from the voltage controlled oscillator 14 is applied to the inversion reset terminals (rb) of the flip-flops 113 and 114 such that two control signals dn1 and dn2 are generated, respectively. According to the two signals up1 and up2, the OR gate 115 generates a control signal up for controlling the charge pump 12 (refer to FIG. 2(a)). Similarly, the OR gate 116 generates a control signal dn for controlling the charge pump 12 according to the two signals dn1 and dn2 (refer to FIG. 2(b))
Referring to FIG. 1, the voltage Vd is substantially controlled by the signals (up, dn). In other words, the variation of the control voltage Vd is related to the phase error xcex8e. FIG. 4 illustrates the relation between the variation of Vd and the phase error xcex8e. As shown in FIG. 4, when the data signal data has a phase lagging behind the clock signal CKvco, the smaller the phase error xcex8e is, the more the voltage Vd varies. Therefore, phase error xcex8e is theoretically supposed to approximate to zero and closely moves around the origin when the phase-locked loop is going to enter a phase-locked state. However, due to the above phenomenon, when the data signal data of the phase-locked loop has a phase lagging behind the clock signal CKvco, an obvious variation of Vd will be generated, which leads to clock jitter. And, the tolerance for data random jitter becomes worse. In other words, it is difficult to reduce the clock jitter for conventional phase-locked loops, large data random jitter is thus unaccepted.
It is therefore an object of the present invention to provide a multi-phase-locked loop without dead zone, which can reduce clock jitter and provide higher tolerance for data random jitter.
Another object of the present invention is to provide a multi-phase-locked loop without static phase error.
The present invention is characterized by a multi-phase-locked loop which can generate a plurality of multi-phase clock signals by a multi-phase voltage controlled oscillater to detect the transition edge of the data signal data. Accordingly, multiple sets of control signals (upk/dnk) are generated. Therefore, phase error xcex8e and voltage Vd of the multi-phase-locked loop can be adjusted to be nearly linear according to the output control signals. This prevents the multiphase-locked loop from having dead zone. Furthermore, the clock jitter can be reduced and provide greater tolerance for data random jitter.
To achieve the aforementioned object, a multiphase-locked loop for data recovery in accordance with the invention includes a phase detector, a charge pump, a loop filter and a voltage controlled oscillator (VCO).
The phase detector is constituted by N phase detection units (U1, U2, . . . , UN, N is even, Nxe2x89xa74). The phase detection units are connected in cascade configuration, and each of the phase detection unit contains a data signal input terminal for receiving the data signal from outside; a clock signal input terminal for receiving the multi-phase clock signals (CK1, CK2, . . . , CKN) from outside; a delay signal input terminal for receiving the delay signal output from another phase detection unit; a delay signal output terminal for outputting the delay signal; and a charge/discharge control signal output terminal for outputting charge/discharge control signals. Each phase detection unit generates a delay signal (D1, D2, . . . , DN) according to the input data signal and the complement of the multi-phase clock signal.
The delay signal (Dj+1) generated by the (j+1)th phase detection unit is applied to the jth phase detection unit via the jth delay signal input terminal. The delay signal (D1) generated by the first phase detection unit (U1) is applied to the Nth phase detection unit (UN) via the Nth delay signal input terminal. In addition, the jth phase detection unit (Ujxe2x80x21xe2x89xa6jxe2x89xa6Nxe2x80x2j is an integer) generates control signals (dn1, dn2, . . . , dnN/2, upN/2, . . . , up2) for the charge/discharge operations according to the delay signal (Dj) from the jth phase detection unit, the delay signal (Dj+1) from the (j+1)th phase detection unit, and the multi-phase clock signal (CKj) which is applied to the jth phase detection unit. However, the Nth phase detection unit (UN) generates a charge control signal (up1) according to the delay signal (DN) from the Nth phase detection unit, the delay signal (D1) from the first phase detection unit, and the multi-phase clock signal (CKN) which is applied to the Nth phase detection unit.
The charge pump is constituted by N/2 charge and discharge units (CP1, CP2, . . . , CPN/2), wherein the kth (1xe2x89xa6kxe2x89xa6N/2) charge and discharge unit (CPk) receives the kth charge/discharge control signal (upk/dnk) from the above mentioned phase detector and generates a charge/discharge current Ichk, which equals to (wkxc3x97upkxe2x88x92wkxc3x97dnk)Iss, wherein wk is a weighting value; Iss is a fixed current value; and w1 less than w2 less than  . . .  less than wN/2. The total charge/discharge current (Ich) output from the charge pump equals to Ich1+Ich2+ . . . Ichk+ . . . +IchN/2.
The VCO described above is a multi-phase VCO, it outputs N multi-phase clock signals (CK1, CK1 . . . CKN). These signals are applied to the phase detectors described above, respectively.
Under the circumstance described above, the phase difference between CKj+1 and CKj is 2xcfx80/N.
The multi-phase clock signal (CKj+1) which is applied to the (j+1)th phase detection unit (Uj+1) and the multi-phase clock signal (CKj) which is applied to the jth phase detection unit (Uj). In accordance with the invention, the relation between the phase error xcex8e and the voltage Vd of the phase-locked loop can be adjusted to be nearly linear by employing these control signals. Therefore, a phase-locked loop without dead zone can be derived, which can reduce clock jitter and enhance the tolerance for data random jitter.